The construction of a signalling system and the creation of a signal exchange tolerant to occurrent errors in a circuit board or bus arrangement are known to the art in several different forms and constitute a basic requisite for the functioning of a complicated electronic system.
Errors in digital data systems are practically unavoidable and are due, at least partly, to the complexity of the circuits and circuit arrangements used and the complexity of associated electronic and electromechanical components.
By way of an example of the earlier standpoint of techniques in the present context, reference is made to International Patent Publication WO 94/03901 (International Patent Application PCT/US93/07262), which illustrates and describes in error-tolerant, high-speed bus system in an integrated circuit application (wafer scale integration). In this known construction, the bus arrangement includes a plurality of bus lines coordinated in a number of sections or segments and mutually linked via programmable bus couplers. The segments are mutually identical and each segment contains thirteen signal lines.
The International Patent Publication WO 94/14026 (international Patent Application PCT/US93/11343) teaches a data collecting system which utilizes a plurality of parallel data buses (A, B, C) connected to a central control unit (10) and each sensor (14, 15, 16) can be connected to the central control unit (10) over any one of the data buses, through an addressing procedure.
An error in one of the data busses (A, B, C) creates conditions under which the faulty data bus is blocked or by-passed, by using a faultless parallel data bus. The European patent application, Publication EP-A2-0 065 273 teaches a system for mutually coupling a plurality of data systems with the aid of a bus system which has information conductors and control conductors. This publication recommends that the requisite smallest number of control conductors shall be increased manifold, in order to obtain rapid notation of an error and a simple error tolerance.
European Patent Pulibcation EP-B1-0 077 153 teaches digital equipment and methods for achieving essentially continuous operation even when several error conditions occur.
This latter publication proposes that the bus structure within each processor module shall include duplicated bus structures, and that each functional unit may have a duplicated partner unit. When establishing an error, the process module is instrumental in isolating the bus or the unit that causes the error, by allowing information to be transferred to the other unit or module.
U.S. Pat. No. 4,412,281; 4,486,826; 4,453,251; 4,597,084; 4,750,177; and 5,247,522 also form part of the earlier standpoint of techniques.
With regard to magazine-related bus arrangements, to which technique the present invention refers, it is known from European Patent Publication EP-A2-0 302 351 to create conditions for building a number of complete bus arrangements in the backplane and to coordinate one or more of said bus arrangements with different circuit boards.
In this respect, it is necessary for the number of coordinated contact springs to correspond with the number of bus conductors in each coordinated group and for the number of bus conductors to be chosen to correspond to the least possible number of bus conductors so as to provide parallel signal transmission of the digital signals under non-redundant conditions.
The disclosures made in European Patent Publications EP-A1-0 488 057, EP-A2-0 301 499 and EP-A2-0 226 765 and the U.S. Pat. Nos. 5,006,961, 4,988,180 also belong to the earlier standpoint of techniques.
When summarizing the aforesaid known prior art, it can be said that it is known to create redundant bus arrangements in magazine-related bus arrangements of the kind to which the present invention relates, by using duplicated by triplicated complete bus arrangements or bus arrangements increased to an N-value, each exhibiting non-redundant and non-error-tolerant conditions.
Duplicated bus arrangements are chosen in those coupling arrangements with which it has been elected to substitute a utilized complete bus arrangement with a reserve complete bus arrangement when the first mentioned bus arrangement is afflicted with an error of a more or a less serious nature.
Triplicated bus arrangements have been used in applications where the requirements placed on reliability are extremely high and where is high error tolerance is required.